This invention pertains to adaptive and programmable improvement of jitter tolerance margins in feed-forward data recovery systems using statistical correlating digital phase-filtering techniques.
High speed digital communications networks require very accurate time synchronization throughout the network. This is accomplished by incorporating xe2x80x9cclock-recoveryxe2x80x9d circuits in key network components such as add/drop multiplexers, digital cross-connects, regenerative repeaters, etc. Such circuits extract timing signals embedded in the transmitted data. The extracted timing signals are used to control sampling and retiming of the received data. However, noise can cause the period of a received data signal to fluctuate or xe2x80x9cjitterxe2x80x9d. The extracted timing signals must remain in synchronization with the data, irrespective of jitter.
For purposes of this invention, a clock recovery circuit""s xe2x80x9cjitter tolerancexe2x80x9d is representative of the maximum amount of jitter that can be imposed on a timing signal processed by the circuit without impairing the circuit""s ability to produce a jitter-free replica of the timing signal. Typical clock recovery circuits have very high jitter tolerance (exceeding 1 Unit Internal (UI)) at lower jitter frequencies, but have significantly degraded jitter tolerance when processing signals having high frequency jitter content.
Prior art clock-recovery circuits are typically based on phase-locked loop (PLL) or surface acoustic wave (SAW) filters, with PLLs being more common in view of the high cost of SAWs. Analog PLLs, typically comprising a phase detector, voltage-controlled oscillator (VCO) and a low pass filter, are undesirable in spite of their highly accurate performance, due to their relative complexity, large power consumption and large integrated circuit surface area requirements.
Digital data recovery systems, such as feed-forward over-sampled architectures have been developed to reduce the large power consumption and integrated circuit surface area requirements of analog systems. Prior art over-sampled architectures can perform very high speed phase detection with good low frequency jitter margins. However, such architectures are subject to significant degradation of jitter tolerance if subjected to high frequency jitter and low transition data.
More particularly, high speed phase tracking at very high frequencies is susceptible to unwanted tracking of uncorrelated high frequency noise components such as duty-cycle distortion, pattern dependent jitter (also known as inter-symbol interference or ISI), high frequency noise on data over-sampling clock phases (resulting in abrupt movement of the reference phases) or glitchy transition detection (due mostly to metastability problems in the front-end samplers). Most such noise components bear no correlation to the relatively lower frequency deterministic component of noise or phase change.
Prior art systems which are incapable of distinguishing between such high frequency uncorrelated noises and their lower frequency deterministic counterparts are error prone. The jitter tolerance of such systems is reduced well below the theoretical maximum of (1-phase quantization step) UI peak-to-peak, to a theoretical minimum of (phase quantization stepxe2x80x94non-idealities) UI peak-to-peak. phase quantization step (or phase quantization noise) is the minimum phase step which cannot be further broken down and distinguished by the system. In a q-times over-sampled architecture, the phase quantization step is qxe2x88x921 UI peak-to-peak. non-idealities (which tend to further reduce jitter tolerance) include factors such as input offset at the data sampler""s front end, duty cycle distortion on the data, etc.
FIGS. 1, 2 and 3 illustrate the prior art""s significant degradation of jitter tolerance at high speed. FIG. 1 depicts a conventional feed-forward over-sampled data recovery scheme with a four-bit segment of an ideal, jitter-free data signal 10 representing the bit pattern xe2x80x9c1010xe2x80x9d. Each four-bit segment is 5-times over-sampled (i.e. q=5), reducing the data rate required in the subsequent pipelined processing circuitry by a factor of four, with the five sampling clock phases 12 (i.e. xcfx862, xcfx863, xcfx864, xcfx865) ideally being equally spaced apart by 0.2 UI over the four bit segment. FIG. 3 is a phase-circle diagram depicting a 1 UI bit period divided into five phase periods xcfx861, xcfx862, xcfx863, xcfx864, xcfx865 arranged in a circle, with bit boundary 31 shown, by way of example only, between xcfx861 and xcfx865. Each phase period corresponds to 0.2 UI, as noted above.
Returning to FIG. 1, xe2x80x9cbit 1xe2x80x9d is sampled five times at sampling clock phases xcfx8611, xcfx8621, xcfx8631, xcfx8641, and xcfx8651; xe2x80x9cbit 2xe2x80x9d is sampled five times at sampling clock phases xcfx8612, xcfx8622, xcfx8632, xcfx8642, and xcfx8652; xe2x80x9cbit 3xe2x80x9d is sampled five times at sampling clock phases xcfx8613, xcfx8623, xcfx8633, xcfx8643, and xcfx8653; and, xe2x80x9cbit 4xe2x80x9d is sampled five times at sampling clock phases xcfx8614, xcfx8624, xcfx8634, xcfx8644, and xcfx8654. The twenty resultant over-sampled bits are exclusive-or""d, in adjacent pairs, by one of twenty exclusive-or gates 14 to produce, at outputs 16, twenty binary signals representative of the 0-to-1 and 1-to-0 bit transitions in signal 10. For example, the leftmost exclusive-or gate shown in FIG. 1 produces a xe2x80x9c1xe2x80x9d output signal representative of the 0-to-1 bit transition in the trailing edge portion of bit 1 during sampling clock phase xcfx8611, etc.
The corresponding phase portions of bit transition output signals 16 are summed to produce a weighted sum for each of the five phases implicit in the aforementioned 5-times over-sampling of signal 10. Specifically, combiner 18 produces an output signal xcfx861sum representative of the sum of the 1st phase over-sampled portions xcfx8611, xcfx8612, xcfx8613, xcfx8614 of bits 1, 2, 3 and 4 respectively; combiner 20 produces an output signal xcfx862sum representative of the 2nd phase over-sampled portions xcfx8621, xcfx8622, xcfx8623, xcfx8624; combiner 22 produces an output signal xcfx863sum representative of the 3rd phase over-sampled portions xcfx8631, xcfx8632, xcfx8633, xcfx8634; combiner 24 produces an output signal xcfx864sum representative of the 4th phase over-sampled portions xcfx8641, xcfx8642, xcfx8643, xcfx8644; and, combiner 26 produces an output signal xcfx865sum representative of the 5th phase over-sampled portions xcfx8651, xcfx8652, xcfx8653, xcfx8654.
The five weighted summation signals xcfx861sum, xcfx862sum, xcfx863sum, xcfx864sum and xcfx865sum are input to 5-way comparator 28 which determines the summation signal having the greatest weight and outputs a signal representative thereof to data selector 30. As FIG. 1 clearly shows, in the absence of jitter on signal 10, combiner 18 receives four xe2x80x9c1xe2x80x9d input signals, whereas each of combiners 20, 22, 24 and 26 receive four xe2x80x9c0xe2x80x9d input signals. Accordingly, the summation signal xcfx861sum produced by combiner 18 clearly outweighs the summation signals produced by any one of combiners 20, 22, 24 and 26. Consequently, 5-way comparator 28 correctly outputs to data selector 30 a signal representative of the fact that the 0-to-1 and 1-to-0 bit transitions in signal 10 occur during the 1st phase (i.e. xcfx861) over-sampled portions xcfx8611, xcfx8612, xcfx8613, xcfx8614, of bits 1, 2, 3 and 4 respectively, thereby facilitating accurate recovery of signal 10 by subsequent processing circuitry (not shown). If 5-way comparator 28 determines that two phases have equally high weighting, it invokes an arbitration scheme to select one of those two phases.
Now consider FIG. 2, which is identical to FIG. 1 except that a jittered version 10A of data signal 10 is to be recovered. In this case, combiner 18 receives four xe2x80x9c0xe2x80x9d input signals; combiner 20 receives three xe2x80x9c0xe2x80x9d input signals and one xe2x80x9c1xe2x80x9d input signal; combiner 22 receives three xe2x80x9c0xe2x80x9d input signals and one xe2x80x9c1xe2x80x9d input signal; combiner 24 receives two xe2x80x9c0xe2x80x9d input signals and two xe2x80x9c1xe2x80x9d input signals; and, combiner 26 receives four xe2x80x9c0xe2x80x9d input signals. Consequently, 5-way comparator 28 incorrectly outputs to data selector 30 a signal indicating that the 0-to-1 and 1-to-0 bit transitions in signal 10 occur during the 4th phase (i.e. xcfx864) over-sampled portions xcfx8641, xcfx8642, xcfx8643, xcfx8644 of bits 1, 2, 3 and 4 respectively, resulting in inaccurate recovery of signal 10 by data selector 30.
This invention utilizes a digital phase filter which accumulates phase transition statistics, discriminating between correlated (i.e. deterministic) and uncorrelated phase noise to facilitate filtration (i.e. suppression or rejection) of uncorrelated phase noise, thereby improving jitter tolerance and in turn improving the data recovery capability. Unlike prior art feed-forward data recovery systems, the invention achieves high jitter tolerance notwithstanding large amounts of high frequency noise and low transition density data patterns. The invention is capable of jitter tolerance close to the theoretically attainable limit (i.e. comparable to the performance of analog PLLs) but with significantly lower power consumption and reduced integrated circuit surface area.
The invention improves over-sampled timing signal jitter tolerance in a q-times over-sampled architecture. The over-sampled timing signal is phase-sampled to produce a plurality of input phase samples xcfx86in, where xcfx86inxcex5{xcfx861, xcfx862, . . . , xcfx86q}. An output phase value xcfx86out=xcfx86in is initialized for each input phase sample xcfx86in. A difference vector di is then derived for each input phase sample xcfx86in, where di=Fj(n,k). F denotes a vector operation, n is the number of input phase samples, k is a pre-defined threshold value, and j represents a filter order value. A predefined scaling coefficient ai is applied to each difference vector di to produce a corresponding set of scaled difference vectors ai di. The scaled difference vectors are then summed:       d    j    =            ∑              i        =        1            n        ⁢                  a        i            ⁢                        d          i                .            
The output phase value xcfx86out is either incremented by 1 if dj greater than k; or decremented by 1 if dj less than xe2x88x92k; and maintained unchanged if xe2x88x92kxe2x89xa6djxe2x89xa6k. Finally, the output phase value xcfx86out is selected to represent the input phase sample xcfx86in.
In a first order filter embodiment of the invention, j=1 and ai=1 for all i=1, . . . , n.
The vector operation F may comprise assigning a value 1 to the difference vector di if xcfx86in greater than xcfx86out; assigning a value xe2x88x921 to the difference vector di if xcfx86in less than xcfx86out; and, assigning a value 0 to the difference vector di if xcfx86in=xcfx86out.
The parameters j, n and k may be varied (programmably or otherwise) to attain a desired jitter tolerance value. Adaptive performance can be attained by deriving a pluralityN of difference vectors diN for each input phase sample xcfx86in, where diN=FjN(nN,kN), and combining selected ones of the difference vectors diN to attain a desired jitter tolerance value.
Alternatively, adaptive performance can be attained by processing a selected number of the difference vectors to produce a jitter spectrum representative of statistically significant variation in the difference vectors, then varying j, n, k and ai as a function of the jitter spectrum to adaptively attain a desired jitter tolerance value. Jitter tolerance can be further improved by monitoring the bit error rate of the output phase value xcfx86out, and, increasing the number of the difference vectors used to produce the jitter spectrum if the bit error rate exceeds a pre-defined value.